Call for Papers

Artificial Intelligence (AI) and Machine Learning (ML) techniques have become the de facto engines of scientific discovery, automation, and economic growth. With rapid advances in large-scale models and accelerated computing, the global technology ecosystem continues to shift toward AI-driven workloads. The storage, computation and communication demands for these workloads are increasing at an unprecedented pace.
Over the past nine editions, the CogArch workshop has brought together experts exploring novel design ideas for cognitive systems. This workshop capitalizes on the synergy between industrial and academic efforts to deepen our understanding of cognitive architectures and the key concepts that shape them. This year’s edition emphasizes the architectural challenges that emerge as large AI models scale from single-die systems to multi-chip, multi-node clusters, where performance is increasingly dominated by collective communication workloads (e.g., AllReduce, AllGather, ReduceScatter). As LLMs and multimodal foundation models continue to grow in size and complexity, the efficiency of these collective operations becomes a primary limiter of end-to-end performance across training and inference pipelines. This shift necessitates architectural innovations at every layer—from chiplets and on-package interconnects to cluster networks, memory systems, and software-hardware co-design strategies that accelerate synchronization-heavy computation.
The CogArch workshop solicits formative ideas and new architectural directions for AI systems, with particular focus this year on techniques, frameworks, and hardware/software co-design approaches that optimize collective algorithms across chiplets, accelerators, and distributed clusters.

Topics of interest include (but are not limited to):

• Architectures and interconnects optimized for collective communication (AllReduce, AllGather, etc.).
• 2.5D/3D chiplet technologies and advanced packaging for scalable multi‑die AI systems.
• Cluster‑level network fabrics (electrical/optical/hybrid) supporting communication‑bound AI workloads.
• HW/SW co‑design for collective algorithms, parallelism strategies (DP/TP/PP/MoE), and communication scheduling.
• Compiler and runtime support for distributed execution across chiplets, accelerators, and clusters.
• Microarchitectural enhancements for communication efficiency (e.g., in‑network compute).
• Memory and I/O hierarchies for large‑model distributed training and inference.
• Energy‑efficient designs targeting interconnects, synchronization, and communication hotspots.
• Reliability, resilience, and security in multi‑chip and multi‑node AI systems.
• AI‑driven modeling and design tools for performance and communication optimization.
• Prototype demonstrations of communication‑heavy AI workloads (LLMs, MoE models, multimodal systems).

The workshop will consist of regular presentations and/or prototype demonstrations by authors of selected submissions. In addition, it will include invited keynotes by eminent researchers as well as interactive panel discussions to kindle further interest in these research topics.

Submitted manuscripts must be in English of up to 2 pages (with same formatting guidelines as main conference) indicating the type of submission: regular presentation or prototype demonstration. Submissions should be submitted to the following link.

If you have questions regarding submission, please contact us: info@cogarchworkshop.org

Important Dates

• Paper submission deadline: April 17^th, 2026
• Notification of acceptance: May 15^th, 2026
• Workshop date: June 28^nd, 2026

Program Committee

• Pradip Bose, IBM Research
• Alper Buyuktosunoglu, IBM Research
• Karthik Swaminathan, IBM Research
• Augusto Vega, IBM Research